1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device that uses a thin ferroelectric film and more particularly to a 2T/2C type ferroelectric memory wherein one memory cell comprises two ferroelectric capacitors and two MOS transistors.
2. Description of the Related Art
Nonvolatile ferroelectric random access memories (FeRAM) which use ferroelectric materials carry out nonvolatile storage in the direction of the remnant polarization of ferroelectric capacitors. For a 2T/2C type ferroelectric memory, one memory cell comprises two ferroelectric capacitors and two MOS transistors. This memory stores information of 1 bit by means of polarizing the two ferroelectric capacitors in directions opposite to each other.
For example, FIG. 7 shows the composition of a 2T/2C type ferroelectric memory disclosed in U.S. Pat. No. 4,873,664 and Japanese Laid Open Patent Publication A-63-201998.
This conventional ferroelectric memory has bit line pairs comprising positive bit lines 2.sub.1, 2.sub.2, . . . and negative bit lines 3.sub.1, 3.sub.2, . . . , memory cells (MC) 10 arranged in an array shape at the intersection between word lines 1.sub.1 to 1.sub.n, pre-charge circuits 9 one being disposed at each bit line pair, sense amps 8 one being disposed at each bit line pair, a Y-switch circuit 7 that selectively connects the bit line pairs and data line pairs 16.sub.1, 16.sub.2, . . . , data amps (DA) 13.sub.1, 13.sub.2, . . . equal in number to the data line pairs 16.sub.1, 16.sub.2, . . . , and write buffers (WB) 14.sub.1, 14.sub.2, . . . equal in number to the data line pairs 16.sub.1, 16.sub.2, . . .
The memory cells 10 are arranged on the same word lines 11 to 1.sub.n. The memory cells 10 which are arranged on the same word lines 1.sub.1 to 1.sub.n comprise one word that forms a read and write access unit of storage data.
The latch type sense amp 8 amplifies a minute potential difference between two lines of respective pairs and the line exhibiting a lower potential is set to 0V and the line exhibiting a higher potential, to VCC. Therefore, the sense amp activation signal 12 changes to the power supply voltage (VCC) from 0V.
Bit line pairs that comprise one word are selectively connected to the data line pairs such as 16.sub.1, 16.sub.2, . . . through the Y-switch circuit 7. This data line pair 16.sub.1, 16.sub.2 includes two data lines, positive and negative, which correspond to the bits which comprise the word on a one-to-one basis.
The Y-switch circuit 7 connects the designated bit line pair and data line pair only during the period when a Y-switch activation signal 19 is at the VCC level. On each of data line pairs are connected a complementary input of data amps 13.sub.1, 13.sub.2, . . . and a complementary output of write buffers 14.sub.1, 14.sub.2, . . .
The data amps 13.sub.1, 13.sub.2, . . . amplify each data appearing on the data line pairs and then externally output the data as output data 28.sub.1, 28.sub.2, . . .
The write buffers 14.sub.1, 14.sub.2, . . . output input data 29.sub.1, 29.sub.2, . . . supplied from an external source to the data line pairs 16.sub.1, 16.sub.2, . . . during the period when a write activation signal 17 is VCC. In particular, when the Y-switch circuit 7 is active and the sense amps 8 are active, the data that was output to the data line pairs 16.sub.1, 16.sub.2, . . . is output to the sense amps 8 which are connected through the Y-switch circuit 7.
Referring to FIG. 8, the memory cell 10 is comprised by two ferroelectric capacitors 22, 23 and two N-channel MOS transistors 20, 21.
Hereafter, the memory cell 10 disposed at the intersection of the word line 11 and the bit line pair that comprises and the positive bit line 2.sub.1 the negative bit line 3.sub.1 will be described.
One electrode of the ferroelectric capacitors 22, 23 is connected to the positive bit line 21 or the negative bit line 3.sub.1 through N-channel MOS transistor 20, 21. The other electrode is connected to a plate line 4. Further, the gates of the two transistors 20, 21 are connected to the word line 1.sub.1.
Referring to FIG. 9, a pre-charge circuit 9 comprises N-channel MOS transistors 24, 25. Because this circuit 9 pre-charges the bit line pair to 0V, while the read and write of the data is not carried out in standby, a bit line pre-charge signal 11 is VCC.
Next, the read operation of this conventional ferroelectric memory will be described. At first, the bit line pre-charge signal 11 falls from VCC to 0V then the bit line pair floats at 0V. Next, the word line 11 is at VCC. Then, when the plate line 4 rises from 0V to VCC, a voltage is applied to the ferroelectric capacitors 22, 23 of all the memory cells 10 selected on the word line. This voltage reverses the polarization of one of the ferroelectric capacitors and then by means of supplying a large amount of charge from the ferroelectric capacitors, the voltage of the connected bit lines becomes higher. Thus, because the other ferroelectric capacitor does not reverse its polarization, the voltage of the connected bit lines becomes lower in comparison to the bit line of the opposite side.
Hereafter, in order to simplify the description, the positive bit line (negative bit line) exhibits a higher voltage compared to the negative bit line (positive bit line). In this way, the difference in the voltage that appears on the positive and negative bit lines is amplified by the sense amps 8. By means of this action, the positive bit line (negative bit line) that exhibits a high voltage is VCC and the negative bit line (positive bit line) that exhibits a low voltage is 0V.
Thereafter, the bit line pair (2.sub.1, 3.sub.1) connects to a data line pair 16.sub.1 through the Y-switch circuit 7 at a timing wherein the Y-switch circuit activation signal 19 is active. Finally, the signal that appears on the data line pair 16.sub.1 is amplified by data amp 13.sub.1 and outputs as output data 28.sub.1. Hereupon, because the positive bit line (negative bit line) is at a high voltage, the output data is "1" ("0").
After the data is read, both of the two ferroelectric capacitors 22, 23 are at a high voltage on the plate line 4 side. Because of this, if the voltage on both side is left as is at 0V, the direction of the remnant polarization lines up. In order to read the same data at the next access, it is necessary to write back the data twice. In this conventional ferroelectric memory, the write back is carried out as follows.
At first, with the sense amps 8 in an active state, the plate line 4 falls from VCC to 0V. Next, the sense amps 8 enter an inactive state, the bit line pre-charge signal 11 rises from 0V to VCC and both bit lines are 0V. Lastly, with the word line at 0V, the ferroelectric capacitors 22, 23 separate from the bit line. Before the ferroelectric capacitor that did not reverse its polarization during the read lowers the voltage of the plate line 4, 0V is applied to the bit line side and VCC is applied to the plate line 4 side. When this ferroelectric capacitor lowers the plate line to 0V, both sides become 0V and as shown in FIG. 10, the remnant polarization is maintained at point B in the Q-V plane.
In contrast, when the ferroelectric capacitor that reversed its polarization during the read lowers the voltage of the plate line 4, VCC is applied to the bit line side and 0V is applied to the plate line 4 side. When this ferroelectric capacitor lowers the bit line to 0V, both sides become 0V and as shown in FIG. 10, the remnant polarization is maintained at point A in the Q-V plane. In this ferroelectric memory, the polarization reversal occurs one time due to the write back. By means of this write back operation, reading of the same data is ensured even during a subsequent read.
Regretfully, in this conventional example, an imbalance exists in which the polarization reversal occurs two times in one of the ferroelectric capacitors per each access through the above-mentioned read/write back and in the other ferroelectric capacitor the polarization reversal does not occur. FIG. 11 (a) shows the plot the ferroelectric capacitor follows in the Q-V plane when the polarization reversal occurs two times and FIG. 11(b) shows the plot the ferroelectric capacitor follows in the Q-V plane when the polarization reversal does not occur. In this way, when repeatedly reading data in a conventional 2T/2C type ferroelectric memory, one of the ferroelectric capacitors will repeatedly reverse its polarization. Moreover, a voltage pulse of one direction will be repeatedly applied to the other ferroelectric capacitor.
Next, the write operation of this conventional ferroelectric memory will be described.
Hereafter, a case when writing input data 29.sub.1 to the memory 10 disposed at the intersection between the word line 1.sub.1 and the bit line pair that comprises the positive bit line 2.sub.1 and the negative bit line 3.sub.1 will be described.
During the write operation in the ferroelectric memory, input data 29.sub.1 supplied from an external source is written to a random word. Because ferroelectric memory is a destructive read type memory, the storage data of the memory cell 10 that shares the memory cell 10 to be written to and the word line 1.sub.1 must be protected. Therefore, at first, the storage data of the memory cell 10 on the word line 11 is amplified and latched by the sense amps 8 using a procedure identical to the previously described read operation.
Next, the Y-switch circuit 7 is made active in a state wherein the input data 29.sub.1 is output to the data line pair 16.sub.1 by means of the write buffer 14.sub.1. At this time, the bit line pair (2.sub.1, 3.sub.1) selectively connect to the data line pair 16.sub.1 by means of the Y-switch circuit 7. This connection latches the input data 29.sub.1 to the sense amp 8 connected to the bit line pair (2.sub.1, 3.sub.1) without disturbing the data of the other sense amps 8. Thereafter, the plate line 4 falls, a pre-charge of the bit line to 0V occurs, and the word line 11 falls using a procedure identical to the previously described write back.
Generally, it is known that a ferroelectric capacitor reduces the remnant polarization following the number of times the polarization reversal repeats. This phenomenon is called fatigue. In a ferroelectric memory, if the remnant polarization reduces, the signal voltage output to the bit line during a read will also be reduced. Further, if the bit line signal voltage output to the bit line is made to fall below the input offset voltage of the sense amps then the function as a ferroelectric memory will normally be lost.
When repeatedly reading the same data in the above-mentioned conventional ferroelectric memory, there was a problem in which fatigue would appear concentrated in one of the ferroelectric capacitors with this concentration of fatigue determining the lifespan of the entire ferroelectric memory.